c3000 Project Status
Project File: c3000.ise Implementation State: Placed and Routed
Module Name: C3000
  • Errors:
 
Target Device: xc3s400an-4fgg400
  • Warnings:
 
Product Version:ISE 11.1
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 663 7,168 9%  
Number of 4 input LUTs 3,215 7,168 44%  
Number of occupied Slices 1,953 3,584 54%  
    Number of Slices containing only related logic 1,953 1,953 100%  
    Number of Slices containing unrelated logic 0 1,953 0%  
Total Number of 4 input LUTs 3,294 7,168 45%  
    Number used as logic 2,518      
    Number used as a route-thru 79      
    Number used for Dual Port RAMs 668      
    Number used as Shift registers 29      
Number of bonded IOBs 105 311 33%  
Number of BUFGMUXs 5 24 20%  
Number of DCMs 1 4 25%  
Number of RAMB16BWEs 11 20 55%  
Average Fanout of Non-Clock Nets 4.63      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Sep 12 15:50:32 2015068 Warnings (0 new)7 Infos (0 new)
Translation ReportCurrentSat Sep 12 15:50:38 2015000
Map ReportCurrentSat Sep 12 15:50:47 2015   
Place and Route ReportCurrentSat Sep 12 15:51:22 201504 Warnings (0 new)3 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentSat Sep 12 15:51:28 2015006 Infos (0 new)
Bitgen ReportOut of DateSat Sep 12 13:08:05 201502 Warnings (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 09/12/2015 - 16:15:40