c302 Project Status (12/16/2013 - 21:42:22)
Project File:	c302.ise	Implementation State:	Programming File Generated
Module Name:	C302	Errors:	No Errors
Target Device:	xc3s250e-5pq208	Warnings:	105 Warnings (0 new)
Product Version:	ISE 11.1	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Setup: 0, Hold: 0) (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	615	4,896	12%
Number of 4 input LUTs	2,419	4,896	49%
Number of occupied Slices	1,366	2,448	55%
Number of Slices containing only related logic	1,366	1,366	100%
Number of Slices containing unrelated logic	0	1,366	0%
Total Number of 4 input LUTs	2,479	4,896	50%
Number used as logic	1,718
Number used as a route-thru	60
Number used for Dual Port RAMs	668
Number used as Shift registers	33
Number of bonded IOBs	105	158	66%
Number of RAMB16s	12	12	100%
Number of BUFGMUXs	5	24	20%
Number of DCMs	1	4	25%
Average Fanout of Non-Clock Nets	4.60

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Mon Dec 16 21:41:33 2013	0	73 Warnings (0 new)	16 Infos (0 new)
Translation Report	Current	Mon Dec 16 21:41:38 2013	0	1 Warning (0 new)	0
Map Report	Current	Mon Dec 16 21:41:44 2013	0	17 Warnings (0 new)	3 Infos (0 new)
Place and Route Report	Current	Mon Dec 16 21:42:09 2013	0	14 Warnings (0 new)	3 Infos (0 new)
Power Report
Post-PAR Static Timing Report	Current	Mon Dec 16 21:42:13 2013	0	0	3 Infos (0 new)
Bitgen Report	Current	Mon Dec 16 21:42:20 2013	0	12 Warnings (0 new)	1 Info (0 new)

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 12/16/2013 - 21:42:22